65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
v dd
gnd 40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
v dd
gnd 64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
v dd
gnd
gnd
v dd
gnd
gnd pin
no. i/o 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 i
i
i
i
i
i
i
i
i
i
i
? ? i
i
i
i
i
i
i q12
q11
q10
q9
q8
q7
q6
q5
q4
q3
q2
v dd
gnd
q1
q0
i12
i11
i10
i9
i8 signal pin
no. i/o 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40 i
i
i
i
i
i
i
i
i
i
i
? ? i
i
i
i
i
i
i i7
i6
i5
i4
i3
i2
i1
i0
y12
y11
y10
gnd
v dd
y9
y8
y7
y6
y5
y4
y3 signal pin
no. i/o 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60 i
i
o
o
o
o
? o
o
o
o
? ? o
o
o
o
? o
i y2
y1
p0
p1
p2
p3
gnd
p4
p5
p6
p7
gnd
v dd
p8
p9
p10
p11
gnd
p12
oe signal pin
no. i/o 61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80 i
i
i
i
o
i
i
i
i
i/o
i
i
? ? i
i
i
i
i
i lmt0
lmt1
rnd
smpl
tsto
tsti
ckx
rst
cs
sdat
sadd
ckd
v dd
gnd
ck
sc
lalt
mode0
mode1
mode2 signal CXD8063Q(1/3)
il08d matrix/encoder
?op view
inputs
ck
ckd
ckx
cs
i0 - i12
lalt
lmt0, lmt1
; system clock
; serial interface clock
; switching timing pulse
; chip select (low : active)
; i in (2? complement 12.1 bit)
; line alternate pulse
(high : even, low : odd)
(high : continuous)
; p output limiter mode control mode0 - mode2 ; mode select oe
q0 - q12
rnd
rst
sadd
sc
smpl
tsti
y1 - y12
outputs
p0 - p12
tsto
input/output
sdat ; p output enable control (low : enable)
; q in (2? complement 12.1 bit)
; rounding p output control (high : active)
; reset pulse (low : reset serial i/f)
; serial address
; subcarrier in
; sampling pulse for p output ( )
; test mode control (high : test mode)
; y in (2? complement 12.0 bit)
; p out (2? complement 12.1 bit)
; test
; serial data lmt1 lmt0 l lh h ? 100000000000.0 100000000000.0 011111111111.1 011111111111.1 input ? 100000000000.0 100000000000.0 011111111111.1 011111111111.1 input ? 100000000000.0 000000000000.0 011111111111.1 011111111111.1 input ? 100000000000.0 100000000000.0 011111111111.1 111111111111.1 input mod2
0
0
0
0
1
1
1
1 mod1
0
0
1
1
0
0
1
1 mod0
0
1
0
1
0
1
0
1 mode and function matrix, p = (y+a) x d + (i+b) x e + (q+c) x f + g
not used
rotation i, p = ( y + a) x d + (i + b) x e + (q + c) x (-f) + g
rotation ii, p = ( y + a) x d + (i + c) x f + (q + b) x e + g
not used
not used
encoder (ntsc)
encoder (pal) a, b, c, ...g ; register data from serial data 0
1 ; low level
; high level CXD8063Q(2/3)
42 - 34
31 - 29 12.0 13.0 12.0 12.0 sw3 sw1 0 ? y1 - y12 43 - 46
48 - 51
54 - 57, 59 p0 - p12 limit a 2.10 63 rnd 3 d smpl 28 - 16 12.1 13.1 12.1 12.1 1 i0 - i12 71 sadd to registers
(a?) limit 64 15.1 12.1 limit b 2.13 4 12.1 e 5 f 12.0 6 g 61 lmt0 62 lmt1 -1 sw4 sw2 ? 15, 14
11 - 1 12.1 13.1 12.1 12.1 2 q0 - q12 limit c 2.13 -1 sw5 7 h -1 d
dt serial
control 70 sdat 72 ckd 69 cs 67 ckx 68 rst 60 oe sw1 switch
control 77 sw2 78 sw3 79 sw4 80 sw5 lalt 76 sc mode0 66 65 tsti tsto mode1 mode2 CXD8063Q(3/3)
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